ASIC DESIGN SUPPORT CAPABILITIES

An ASIC is an application specific integrated circuit, which is usually designed to cover a need of functionality or performance (speed, power consumption, dimensions, etc.) that cannot be achieved by a combination of preexistent integrated circuits.

The design of an ASIC implies the interoperability of complex tools. In the figure, it can be observed a simplified flow for a low power mixed-signal ASIC design, where both the digital and analog flow will converge via open access.

Typical ASIC flows will become even more complex when designing ASICs for Space applications. First of all, the designer should take care of the whole qualification flow that the samples will be submitted for, and from the very beginning, this must be taken care with a strong Design For Test (DFT) strategy. As for example, for rad-hard designs, the TID measurements will be made in a very limited time for the samples not to enter in annealing. Therefore, DUT should be designed to match the test setup that can make this possible (e.g. High-End Automatic Test Equipments). Another example of variation from typical ASIC flows is the need of using predesigned and qualified hard-rad libraries (whose performance in many conditions should be well known), hard-rad technologies or even develop your own radiation models for a technology (perform a test chip to model ASIC fabrication technology primitives under radiation).

As ASICs are a fixed design circuit, in other to obtain success with minimized expenses in the first-silicon approach many implications should be considered. This is one of the reasons why it is necessary to have a team of professionals who offer continuous support backed by the space applications experience that only a group like Alter Technology can offer its customers. We offer ASIC consulting but also workforce to cover the punctual needs of experienced designers.

Asic Design Support Offered

• Staff for external workforce or support of ASIC development teams (no ownership of licenses, connection via VPN or similar to design server).
• Designers of over 10 years of experience in ASIC design: Analog, Mixed Signal, and Digital Flows, RF simulation.
• Digital Design and Signoff: Full custom digital layouts, Front-End, and Back-End flow and scripts, RTL development in Verilog or VHDL, functional simulation, constraint development, design for test logic, synthesis, timing analysis, power analysis, behavioral modeling, and verification.
• Custom IC/Analog: DRC, LVS, Custom Layouts, Ocean scripts, Skill Programming, Spectre, Spectre RF, and Spectre AMS simulations, Verilog-A and Verilog-AMS behavioral models, corner and sweeps analysis, Monte Carlo statistical analysis, pre and post layout analysis.
• Optoelectronic design such as CMOS Image Sensors design including pixel design, on-chip processing, and column-parallel ADCs.
• Pre-design mathematical models of the design via Matlab.
• Design For Test (DFx) consulting, particularly for very complex ASIC intended to be tested in High-End Automatic Test Equipment (ATE).

Previous Experience in Enviroments and Technologies

Environments:

– Cadence Design Environment:

• Analog: Virtuoso Analog Design Environment Suite, Virtuoso Layout Suite, etc.
• Digital: Encounter, etc.
• Mixed: both analog and digital, including Spectre AMS
• RF Simulations: Spectre RF

Technologies:

– AMS 0.35 μm normal and opto

– UMC 0.18 μm normal and CIS

– TSMC 65nm Low Power

– Towerjazz 0.18 μm CIS.

– Tezzaron FaStackTM (Chartered 130nm Low Power tiers 3D Integration)