Optimizing Decoupling Capacitors
- Posted by doEEEt Media Group
- On June 24, 2022
- 0
Learn how to optimize decoupling capacitors for the best cost vs. performance using flat target impedance design methods.
Impedance peaks caused by parallel L-C resonances in the power distribution network (PDN) are potential sources of power rail ripple and increased EMI. Bulk capacitors must be selected to ensure power supply stability while high-frequency decoupling must ensure the required bandwidth at the Load.
Simple SPICE simulations fail to account for PCB parasitics and often result in the wrong selection of decoupling capacitors. Utilizing EM models of the PDN and combining them with power supply state-space models and the spectral requirements of the load result in good agreement with measurements.
Optimizing this PDN ecosystem shows that designing for flat impedance is the best way to achieve the lowest noise on the power rail with the minimum number of capacitors.
Related video:
Measuring, Modeling, Simulating Capacitors and Inductors
Simple RLC capacitor and inductor models can result in a design with more capacitors than necessary adding to the design cost, consuming valuable circuit board real estate and degrading the control loop performance.
Source: Picotest
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