MICROCHIP FPGAs External Visual Inspection Considerations
- Posted by Antonio Rodríguez Arenas
- On January 20, 2020
- 0
One of the quality assurance inspections that are performed in EEE parts is an external visual inspection. The applicable method for Microchip FPGAs as well as for other parts with generic specification MIL-PRF-38535 is MIL-STD-883 Method 2009.
When performing external visual inspection in these types, RT FPGAs, there are some tips that have to be considered in addition in order to identify correct results of the inspections.
Mark in the top lid in Proto units:
Proto units have a visible mark on the package lid to be well identifiable that those units are not for flight use.
This mark is performed by the manufacturer.
This mark does not affect hermeticity.
Notch located on lead frame side:
This notch is the result of restraining of the leads done at last production step to guarantee proper planarity for programming.
It will not affect in the process of leads cut and forming.
Bent lead:
Bended lead as seen in the picture is caused by mis-handling of devices.
Before using this part it is needed to restrain the leads otherwise would cause problems in programming, correct sitting in sockets or tooling for lead cut and forming.
Wide experience since 1995 in the field of Space EEE in different areas as Project Manager, Proposals preparation for Governmental and Private companies, contracts negotiation and in the last years EEE Space Procurement Quality Manager, which includes General Product Assurance as defined in ECSS, DLA and other Space standards, Alerts, ESA Alerts Coordinator, Failure Analysis, NCRs management and resolution and responsible for quality assurance of EEE parts procured for several Space projects.
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