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EDAPS 2019
December 16, 2019 @ 8:00 am - December 18, 2019 @ 5:00 pm
IEEE Electrical Design of Advanced Packaging and Systems
The IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)symposium, a flagship event in the Asia-Pacific region, has consistently served as a platform for dissemination of latest research in the areas of electrical design of chip, package, and system. Designers and researchers across the world come forth to share and discuss their work on all aspects of electrical packaging including modeling, design and simulation, fabrication and characterization. This symposium consists of technical paper presentation, poster sessions, industry exhibits, workshops, and tutorials.
The southern city of Kaohsiung is Taiwan’s largest port, its second-largest city, and center of the country’s heavy and petrochemical industries. Despite this, it is a modern urban landscape of airy cafes, wide streets, waterside parks, public transport, bicycle lanes and cultural venues that have embraced and re-imagined the city’s manufacturing past. There are also two swimming beaches within the city area, and 1000 hectares of the almost-pristine forest right on its doorstep.
EDAPS is sponsored by the IEEE Electronics Packaging Society.
EDAPS will be an excellent forum to highlight the latest advances in the high-speed and high-performance semiconductor industry. Engineers and researchers will engage in the 3 full-day conferences and workshop, to be held during December 16-18 in Kaohsiung. The forum offers a great opportunity for sponsorships and for the related companies to build their brands in this leading international platform.
TOPICS
- 3D-ICs/TSVs/Interposers
- Testing on 3D-IC and SiP
- Signal and Thermal Integrity
- Power Integrity/Power Distribution Networks (PDNs)/Ground Noise
- Computational Electromagnetics and Multi-physics Methods for SI/PI/TI Analysis
- Thermal Management Design for 3D-ICs and SiP
- Design and Modeling for High-speed Channels and Interconnects
- High-speed serial links jitter budgeting
- Jitter segregation algorithms and tools
- Time / Frequency Domain Measurement Techniques
- Power supply induced jitter and transfer functions.
- Nanoelectronics for 3D-ICs and SiP
- Machine Learning applied to package
- Active Devices and Circuit Modeling Technologies
- Electronic Packages, SiP/ SoP
- IC and Package Level EMC
- Antennas in Packages (AiP)
- RF/mm-wave and THz Packages
- Miniaturized and Embedded Passives
- Power Electronic Packages
- Advanced Simulation Tools and CAD
- Substrate Technology for Packages and PCBs
- Electrical Design of Flexible Devices and Sensing
- 2-D Materials for 3D-ICs and SiP
- 3-D ICs and SiP Reliability
- Electrical Design for 5G Wireless Communication
- DDR’s Signal and Power integrity considerations
- Others
DEADLINES
- Prospective authors should submit a three-page manuscript by August 5, 2019
- Notification about acceptance will be given by September 20, 2019.
- Accepted papers will be reproduced as-is in the Conference Proceedings.
- In addition, authors of accepted papers will be invited to submit an extended version of their manuscript for a Special Section based on EDAPS-2019 to be published in the IEEE Transactions on components, packaging and manufacturing technology (T-CPMT).
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